The present invention relates to semiconductor memory devices in the form of Magnetic Tunnel Junction (MTJ) cells of the type used as storage elements in Magnetic Random Access Memory (MRAM) devices and more particularly to alignment structures formed therein and methods of manufacture thereof.
MRAM devices are based on arrays of MTJ cells. An MTJ cell is a MagnetoResistive (MR) device also known as a Tunnel Junction (TJ) which consists inter alia of two magnetic films; a Pinned Layer (PL) and a Free Layer (FL) separated by a tunnel barrier layer. The PL of the MTJ cell has an irreversible direction of magnetization as it is pinned or fixed by a variety of techniques. In contrast, the magnetization of the FL of the MTJ cell is programmable to be either parallel or anti-parallel to that of the PL during a “WRITE” operation in which data is stored in a memory cell. A thin tunnel barrier which is typically composed of aluminum oxide (Al2O3) is sandwiched between the PL and FL. The resistance of the MTJ cell depends on the direction of the FL magnetization relative to the direction of the PL magnetization. The state of the MTJ cell is sensed in the “READ” operation by measuring the alternatively high or low resistance level of the MR type of tunnel junction.
MTJ cells comprise spin electronic devices which combine semiconductor technology with magnetic materials and devices. The selective reversibility of spin directions of electrons through reversal of their magnetic moments in the magnetic free-layer stack of an MTJ cell, is employed to provide binary MTJ cells which indicate the presence of data in the form of a “ONE” or the absence of data in the form of a “ZERO.” A typical spin electronic device is a Magnetic Random Access Memory (MRAM) device which includes a conductive wordline array and a conductive bitline array (formed in different metal layers.) The conductive wordline and bitline arrays, which are oriented in transverse (usually perpendicular) directions, sandwich a plurality of separate MTJ cells, which combine to function as a MRAM device.
Commonly assigned U.S. Pat. No. 5,640,343 of Gallagher et al. entitled “Magnetic Memory Array Using Magnetic Tunnel Junction Devices in the Memory Cells” describes a technique of employing a pair of mutually perpendicular arrays of metal wires with a MTJ cell placed at each of the intersections of two wires in the two arrays. The MTJ cell is uniquely addressed in the array of MTJ cells by the two wires that intersect above and below the particular MTJ cell of interest.
Commonly assigned U.S. Pat. No. 6,518,588 of Parkin et al. entitled “Magnetic Random Access Memory with Thermally Stable Magnetic Tunnel Junction Cells” describes an MTJ cell which includes a platinum-manganese (Pt—Mn) antiferromagnetic layer, a pinned ferromagnetic CoFe alloy layer, an alumina insulating tunnel barrier layer, and a free ferromagnetic NiFe alloy layer. The MTJ cell includes an underlayer and a capping layer. The underlayer is a bilayer comprising a low-resistivity alpha-tantalum (Ta) layer formed on a tantalum nitride (TaN) seed layer which is deposited on both an SiO2 insulating material and on a stud which provides an electrical connection to an M2 level word line. The capping layer is a bilayer comprising a TaN layer formed on the tree ferromagnetic layer and an alpha-Ta layer between the TaN layer and an M3 level bit line. Because the studs and metallization layers are preferably formed of copper (Cu), the Ta and TaN must be non-reactive with Cu. Also, the Ta must be non-reactive with Pt—Mn, which is the preferred antiferromagnetic material.
Commonly assigned U.S. Pat. No. 6,933,204 of Sarma et al entitled
“Method for Improved Alignment of Magnetic Tunnel Junction Elements” describes formation of a semiconductor memory array with MTJ elements and a method for exposing a set of pre-existing M2 level alignment marks below subsequently deposited MTJ metallization. The method comprises forming an MTJ stack layer over an optically transparent layer composed of a Tantalum Nitride (TaN) layer formed on a lower metallization level after the pre-existing M2 level copper alignment marks were formed in the lower M2 metallization level. Then a portion of the MTJ stack layer is patterned and opened in the location of the pre-existing alignment marks in the lower metallization level so as to render the pre-existing alignment marks optically visible. The method employs patterning of the MTJ stack layer with respect to the lower metallization level, using the previously patterned, pre-existing optically visible alignment marks, but it does not relate to formation of alignment marks during the formation of MTJ alignment marks, which are required for subsequent processing steps in the manufacture of MTJ memory devices. A hard mask comprising a Titanium Nitride (TiN) layer is formed over the MTJ stack layer. A photoresist material which is used to pattern the MTJ stack layer with respect to the lower metallization level is also used to protect the opened portion of the MTJ stack layer corresponding to the location of the alignment marks. Also an oxide hardmask is shown formed over an exposed portion of the optically transparent layer as a result of the patterning and opening a portion of the MTJ stack layer.
FIGS. 1A-1C are sectional elevational views of an MRAM device 10 in the process of being manufactured in accordance with a prior method of manufacturing MTJ devices.
FIG. 1A shows a sectional elevational view of a prior art MRAM device 10 in an intermediate stage of the process of manufacture thereof. The device 10 comprises a lower Inter Level Dielectric (ILD) substrate layer 12 in the upper surface of which, electric conductors 14 have been formed for providing electrical interconnections between features within the device 10. A via level (VA) ILD layer 16 composed of a refractory material, e.g. a bilayer of tantalum over tantalum nitride, has been formed on the top surface of the lower ILD substrate layer 12. A via 15 is shown formed on the top surface of one of the electric conductors 14. A bottom stack conductor layer 136, which is shown to be composed of Ta/TaN, is formed over the VA ILD layer 16 in electrical contact with the via 15 and one of the conductors 14 therebelow. An MTJ stack 137 of layers of material to be formed into TJ devices is formed on the top surface of the bottom stack conductor layer 136. On the top surface of the MTJ stack 137 is an electrically conductive hard mask layer 148 comprising TiN/TaN layers. The electrically conductive hard mask layer 148 can be composed of a hard mask material such as Ti, TiN, Ta, TaN, W and the like, but is not limited to refractory metals and their alloys, as will be well understood by those skilled in the art.
A multiple feature Lithographic Patterning Level (JA) level mask 147 is formed on the top surface of the electrically conductive hard mask layer 148. The JA mask 147 is used to define the Magnetic Tunnel Junction (MTJ) elements. The JA level mask 147 includes a plurality of parallel alignment mark pattern lines 147/A, OVERLAY (O/L) box pattern lines 147/0, and an MTJ element pattern block 147E. The JA level mask 147 is to be employed for patterning several alignment marks, two OVERLAY box features, and an MTJ element 137 as shown in FIGS. 1B and 1C.
The JA level mask 147 is employed at a level in the process of manufacturing which is unique to the manufacturing of MRAM devices. The JA lithographic patterning level requires printing and etching of elliptical or circular shapes on MTJ metal stack 137. Unfortunately, there could be a problem with peeling of a plurality of JA alignment mark features 148A, which are shown in FIG. 1C, as metal stacks tend to peel and delaminate after patterning when cast into elongated shapes such as long lines needed in the alignment mark features 148A. Also the top of the MTJ hard mask 148 (e.g. TiN/TaN) in some cases is too rough to allow the alignment optical system of the stepper to detect a clearly identifiable image of the alignment mark features 148A. The JA level mask is employed to pattern the MTJs. The JA alignment mark features 148A combined with the MTJ stacks inside peel/curl up after deionized DI water rinse or subsequent processing. Poor JA marks often require alignment to the bitline to M2 , or VA level rather than alignment to the more preferable alignment to the JA lithographic patterning level.
FIG. 1B shows the device 10 of FIG. 1A after etching away the exposed portions of the hard mask layer 148 and a partial thickness of the MTJ stack top layers 137 leaving the plurality of parallel alignment mark features 148A, two parallel OVERLAY Box features 148O, and an MTJ element feature 148E below the plurality of parallel alignment mark pattern lines 147A, the two parallel OVERLAY Box pattern lines 147O, and the MTJ element pattern block 147E of the JA level mask 147.
FIG. 1C shows the device 10 of FIG. 1B after stripping of the JA level mask 147 including the parallel alignment mark pattern lines 147A, the OVERLAY Box pattern lines 147O, and the MTJ element pattern block 147E. The alignment mark features 148A, two parallel OVERLAY Box features 148O, and the MTJ element feature 148E remain exposed after the step pf stripping JA level mask 147.
FIG. 2A is a photomicrograph showing a magnified plan view of an MRAM composed of MTJ elements with alignment marks formed as shown in FIG. 1C.
FIG. 2B is a further magnified view of a portion of the photomicrograph shown in FIG. 2A with the ellipse of dots around alignment marks which could potentially be damaged by peeling.
FIG. 3 shows a sectional elevation of prior art MTJ structure 130 comprising a dielectric substrate 132 covered by an M2 conductive line 134 (i.e. a bitline or a wordline) providing electrical connections to a plurality of sets of MTJ stack top layers 137 thereabove. Each of the sets of MTJ stack top layers 137 comprises the pinned magnetic films ML1 film 140 (magnetically pinned by an AntiFerroMagnetic (AFM) film 138,) the free magnetic ML2 film 146, non-magnetic films 136/148 and a tunnel barrier layer (TBL) 142 between the ML1 film 140 and the ML2 film 146. Conventionally, the ML1 and ML2 magnetic films 140 and 146 are composed of ferromagnetic alloys of combinations of Co, Fe and/or Ni, etc. The various non-magnetic films of a bottom cap adhesion layer 136 and a hard mask top cap layer 148 are refractory metals and/or a nitride thereof such as Ta, Ti, TiN, and TaN or their compounds. The MJT stack 137 is typically bounded on the bottom by a diffusion barrier/bottom cap 136 and on the top by the diffusion hard mask barrier top cap 148. The complex stack with several interfaces is believed to be the cause for such stress induced peeling of material in the regions of alignment marks referred to above.
Referring again to FIG. 3, the bottom cap adhesion layer 136 is formed on the top surface of the M2 conductive line 134. The set of multi-layered MTJ stack top layers 137 is formed on top of the bottom cap adhesion layer 136. The MTJ stack top set of layers 137 includes from bottom to top an antiferromagnetic (AFM) layer 138, shown in FIG. 3 as PtMn, FeMn, IrMn, or CrPtMn, a magnetic pinned-layer (ML1 ) stack 140, shown as CoFe or NiCoFe, a tunnel barrier layer (TBL) 142, shown as Al2O3, a magnetic free-layer (ML2 ) stack 146, shown as CoFe/CoFeB, CoFe/NiB or CoFe/NiFeB TaN/TiN, and a diffusion barrier, hard mask top cap layer 148, shown as TaN/TiN on top. The device 130 typically includes the following layers listed in order, from the bottom up: the bottom cap, adhesion layer 136, typically including 5 nm to 10 nm of TaN and/or Ta, the relatively thick AFM layer 138, illustratively including a 20 nm thick layer of PtMn, FeMn, IrMn or CrPtMn. Next is the ferromagnetic “reference” layer or set of layers ML1 stack 140 formed overlying and pinned by the AFM layer 138 comprised of films such as CoFe, NiFe or NiCoFe, which may be interspersed with a nonmagnetic coupling layer such as Ru or TaN that is used to reduce offsets from demagnetization fields. A representative thickness of such a ML1 reference layer(s) is 2 to 5 nm. The foregoing layers make up the pinned layer of such an MTJ device 130. The purpose of the AFM layer 138 is to fix the ferromagnetic reference layer(s) in ML1 stack 140 so that they will not switch magnetization direction during normal operation, thus providing a reference against which to compare the free layer magnetization direction of the ML2 layer 146 which will be switched between “ZERO” and “ONE” (or the reverse thereof) during normal operation of such an MRAM memory device.
The Tunnel Barrier Layer (TBL) 142 of this tunneling MR device 130 comprises a thin dielectric layer deposited onto the top surface of the ML1 stack 140, i.e. the magnetic pinned-layer. Typically, the TBL 142 is formed of an oxide of aluminum, such as including or similar to aluminum oxide (Al2O3) having a thickness of about 1 nm. Other materials available for use as the TBL 142 include oxides of magnesium and other metals, oxides of silicon, nitrides of silicon, and carbides of silicon; as well as oxides, nitrides and carbides of other elements, or combinations of elements and other materials including or formed from semiconducting materials which provide MR tunneling effects as will be well understood by those skilled in the art.
The free-layer ML2 stack 146 that is formed over the tunnel barrier layer 142 may comprise a layer of nickel-iron (NiFe) having a thickness of about 5 nm. In an alternative embodiment, the ML2 stack 146 can be formed of more than one such ferromagnetic layer to enhance performance or manufacturability. Suitable alternative materials include CoFe/CoFeB, CoFe/NiFe, CoFe/NiFeB, Fe, and equivalent free layer materials or a combination of them. That is to say that, NiCoFe, amorphous CoFeB, and similar ferromagnets can be used in place of NiFe as the ferromagnetic portion of the ML2 stack 146.
Thereafter, a conductive barrier top cap layer 148 of tantalum nitride (TaN) or titanium nitride (TiN) having a thickness of about 100 nm is deposited. The conductive barrier top cap layer 148 serves to protect the free-layer ML2 stack 146 during subsequent processing and to provide adhesion for one or more subsequently formed layers. Multiple layers may be separated by non-magnetic layers like TaN or Ru. These layers typically range in thickness from 2 to 10 nm.
The diffusion barrier, hard mask top cap layer 148 is formed on top of the ML2 layer 146 forming the top surface of the layered stack top layers 137. In the simplest embodiment, the hard mask cap layer 148 is formed from a conductive material such as tantalum nitride (TaN) or titanium nitride (TiN). An M3 conductive line 149 is formed over the hard mask cap layer 148 for providing the other electrical connection to the MTJ stack top layers 137.
W. Reohr et al. “Memories of Tomorrow,” IEEE Circuits & Devices Magazine, pp 17-27 (September 2002) describes a one-transistor-one-MTJ memory cell embodiment of this technology expected to have high write endurance and smaller cell size than SRAM devices and shows an MRAM with arrays of word and bit lines connected to MTJ devices.
S. Tehrani et al “Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions;”, Proc. of the IEEE, Vol. 91, no. 5, pp 703-714 (May 2003) states that MRAM devices have a large MR effect so that the resistance thereof depends on its magnetic state. Typical MRAM cells are bistable so they can be written to a high or low resistance state and retain that state without any applied power.
B. N. Engel et al., “The Science and Technology of Magnetoresistive Tunneling Memories,” IEEE Trans. On Nanotech., Vol. 1, No. 1, pp 32-38 (March 2002) states that the advantages of MRAM devices include nonvolatility, high-speed operation and unlimited read and write endurance, enabled by the ability to deposit high-quality, nanometer scale tunneling barriers that display enhanced MR response embodied in a 256-kb memory chip. The MRAM module, is inserted in the Back-End-Of-Line (BEOL) interconnect using four additional lithography steps.
A. R. Sitaram et al. “A 0.18 μm Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications”, Proc. of the VLSI Symposium pp 15-16 (2003) describes alignment of subsequent mask levels to MTJs shows a schematic diagram of an FET MRAM cell with a via VA connecting from an FET through a local interconnect line MA to an MTJ which is connected at the other end to a bit line.
An engineering challenge in inserting MRAM devices during Back End Of Line (BEOL) semiconductor processing of Complementary Metal Oxide Semiconductor (CMOS) integration, is encountered in attempting to provide lithographic alignment of MTJ structures to the metal level therebelow. In most conventional BEOL processing, intermediate dielectric films formed over alignment marks are optically transparent. Since those dielectric films are transparent the stepper machines used to expose devices with accurate alignment of masks to workpieces are enabled by using optical sensors to detect the location of the alignment marks formed on the metallization level below such dielectric films. However, when a MTJ metal stack is opaque there is the problem that the alignment marks of the metal level therebelow are not visible.
U.S. Pat. No. 6,858,441 of Neutzel et al entitled “MRAM MTJ stack to conductive line alignment method” teaches techniques for providing alignment of MTJ devices to levels of metallization therebelow.
As typical in the state of the art, the alignment marks and overlay boxes (collectively referred to as alignment marks from here onwards) are formed lithographically and etched simultaneously as the MTJ elements as shown in FIGS. 1A and 1B. The MTJ elements are typically elliptical elements of various aspect ratios. The alignment marks are on the other hand long lines that are several microns in length. Whereas the MTJ stack is conducive to be cast into such oblong elements. It tends to peels and deform when cast into long features as in the alignment marks as in data from FIGS. 2A and 2B.
The variability introduced into the scattering of the laser light used by steppers to sense the alignment marks could contribute to poor alignment.